1. Technical Field
The present invention relates generally to a semiconductor apparatus, and more particularly, to a three-dimensional (3D) semiconductor apparatus.
2. Related Art
A semiconductor apparatus is verified through a variety of tests before being shipped as a product. In order to reduce the test time and increase test efficiency, a compression test is generally performed. The compression test is performed, for example, by compressing a plurality of data and detecting the level of the compressed data. According to the number of data to be compressed, the test time may vary.
Recently, in order to highly integrate a semiconductor apparatus, a 3D semiconductor apparatus is being developed. The 3D semiconductor apparatus is formed according to such a method that stacks and packages a plurality of chips within one package. According to a known art, the 3D semiconductor apparatus includes two or more chips which are stacked vertically, and thus may achieve a high integration in the same space.
A variety of methods may be applied to implement the 3D semiconductor apparatus. In one of the methods, a plurality of chips having the same configuration are stacked, and then coupled to each other through a wire such as a metal line so as to operate as one semiconductor apparatus.
Furthermore, a through via method, e.g., a through silicon via has been recently used. In the through via method, a plurality of stacked chips are electrically coupled using a through via formed through the chips. In the semiconductor apparatus using a through via, the respective chips are coupled through the through via formed in a vertical direction. Therefore, it is possible to more efficiently reduce a package area than the semiconductor apparatus in which the respective chips are coupled through edge interconnections using a wire.
Also, in the case of a 3D semiconductor apparatus which is packaged including a plurality of chips, the test time may be reduced by applying a technology for compression test circuits.